Integration of a Double - Poly silicon Emitter - Base Self - Aligned Bipolar Transistor into a 0 . 5 - pm BiCMOS Technology for Fast 4 - Mb SRAM ’ s
نویسنده
چکیده
The single-polysilicon non-self-aligned bipolar transistor in a 0.5-pm BiCMOS technology bas been converted into a double-polysilicon emitter-base self-aligned bipolar transistor with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance and base-collector capacitance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density , SRAM circuits.
منابع مشابه
Submicron BiCMOS technologies for supercomputer and high speed system implementation
This paper describes submicron process technologies that allow a full implementation of CPU, first level Cache, second level Cache, and the main memory in a BiCMOS approach. CPU Standard Cells up to l00K ECL gate density with embedded CMOS and BiCMOS SRAM, X9 Cache memories, and 1 Meg ECL U0 SRAMs with less than 7ns access time are achieved. INTRODUCTION State-of-the-art BiCMOS technologies are...
متن کاملTCAD based development of a polysilicon emitter transistor in a BiCMOS technology
Continuing advances in silicon integrated circuit technology lead to todays very large scale integrated circuits with several millions of transistors per single chip. High density and low power consumption advantage made CMOS technology to the leading silicon fabrication technology. Over the last decade the demand for higher speed and better analog circuit gave rise to the BiCMOS technology, wh...
متن کاملA Double Self-Aligned Silicon Bipolar Transistor Utilizing Selectively-Grown Single Crystal Extrinsic Contacts
Feasibility is demonstrated for a unique high speed double self-aligned bipolar junction transistor utilizing monocrystalline silicon base contacts. The transistor is designed for use in high-speed analog or digital applications -where reduced parasitic capacitances and resistances are essential. The device design is unique in reducing extrinsic base/collector capacitance over single self-align...
متن کامل7.2 A Highly Versatile 0.18um CMOS Technology With Dense Embedded SRAM
We report on a 3.3V12.5V compatible, 1.5V high performance dense CMOS SRAM technology utilizing a 2.74 um2 6-T Bitcell. This 0.18pm CMOS process with a nominal 0.13pm gate poly and a 30A gate oxide utilizes aggressive interwell isolation, enhanced self-aligned local interconnect, low-K interlevel dielectric, and scaled copper metalization. In addition, the technology allows for low leakage, hig...
متن کاملPulsed bipolar CMOS imager
This paper will describe an active pixel CMOS-compatible imager aimed at high resolution still cameras. We will discuss pixel operation, column sense circuits, serial output, and show results from existing imagers. In this abstract, we show results from a prototype 640x480 imager with 5.9x5.9 μm2 pixels built in 0.8 μm double-poly CMOS with one additional base implant. Active Capacitor-coupled ...
متن کامل